Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to an electrostatic discharge (ESD) protection device for protecting an internal circuit of a semiconductor device from ESD.
When a semiconductor integrated circuit (IC) comes in contact with a charged human body or machine, electrostatic discharge (ESD) charged in the human body or machine may be discharged to its internal circuits through external pins and pads of the semiconductor IC. At this time, a sudden current having high energy may cause severe damage to the internal circuits. In some cases, ESD charged in the semiconductor IC may flow out to the human body or machine due to the contact with the human body or machine and cause damage to the internal circuits.
As illustrated in FIGS. 1A and 1B, in order to protect internal circuits from such damages caused by ESD, most semiconductor ICs are provided with an ESD protection device between a pad and an internal circuit. In general, an ESD protection device uses transistors.
FIGS. 1A and 1B illustrate a conventional ESD protection device. Specifically, an ESD protection device using an NMOS transistor is exemplarily illustrated.
Referring to FIGS. 1A and 1B, the conventional ESD protection device includes a P-type well 12 formed on a substrate 11, a gate 13 formed on the substrate 11, an N-type source region 15 partially overlapped with one end of the gate 13, an N-type drain region 17 spaced apart from the other end of the gate 13 by a desired distance, an N-type drift region 16 surrounding the drain region 17 and partially overlapped with the other end of the gate 13, and a P-type pickup region 14 formed in the well 12. The drain region 17 is coupled to a pad, and the gate 13, the source region 15, and the pickup region 14 are coupled to a ground.
A breakdown phenomenon occurs when a voltage higher than a breakdown voltage (BV) is applied to the ESD protection device having the above-described structure. The lowest voltage of the ESD protection device after the occurrence of the breakdown phenomenon is referred to as a holding voltage (Vh). The breakdown voltage and the holding voltage are the most important parameters in the ESD protection device. The breakdown voltage and the holding voltage are desired to be higher than the power supply voltage in order that the characteristic of the ESD protection device cannot influence the operation of the internal circuit. In addition, the breakdown voltage and the holding voltage are to have a certain margin to cope with external variations.
However, the conventional ESD protection device having the above-described structure has a feature in that a holding voltage is low. Specifically, when ESD current flows into the ESD protection device through the pad, a horizontal parasitic bipolar (HPB) and a vertical parasitic bipolar (VPB) are simultaneously operated to run the ESD current to the ground through a bypass. In the case of the horizontal parasitic bipolar (HPB), the source region 15 and the drain region 17 serve as an emitter, and the well 12 under the gate 13 serves as a base. In the case of the vertical parasitic bipolar (VPB), the source region 15 and the drain region 17 serve as an emitter, and the well 12 under the drain region 17 serves as a base.
At this time, since a base width of the horizontal parasitic bipolar (HPB) which defines a channel length is short, a current gain of the horizontal parasitic bipolar (HPB) is larger than a current gain of the vertical parasitic bipolar (VPB). Thus, there is a concern that the holding voltage of the ESD protection device is reduced.